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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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256KB/512KB BurstRAMTM Secondary Cache Modules for PowerPCTM PReP/CHRP Platforms
The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2104P and MPC2105P utilize synchronous BurstRAMs. The MPC2104P module is configured as 32K x 64 bits and uses two of the 3.3 V 32K x 32 data RAMs. The MPC2105P is configured as 64K x 64 bits and uses two of the 3.3 V 64K x 32 data RAMs. Both modules are in a 178 (89 x 2) pin DIMM format. For tag bits on the 2104P, a 5 V cache tag RAM configured as 8K x 14 for tag field plus 8K x 2 for valid and dirty status bits is used. For tag bits on the 2105P, a 5 V cache tag RAM configured as 16K x 14 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internally to the BurstRAM by the CNTEN signal. Write cycles are internally self-timed and are initiated by the rising edge of the clock (CLKx) inputs. Writes are global with two inputs for reduced loading. Presence detect pins are available for auto configuration of the cache control. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. All of these cache modules are plug and pin compatible with each other. * * * * * * * * * * * * * PowerPC-Style Burst Counter On Chip Pipeline Data I/O Plug and Pin Compatibility Multiple Clock Pins for Reduced Loading All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible Three State Outputs Buffered Addresses to Data RAMs for Reduced Loading Fast Module Clock Rates: Up to 66 MHz Fast SRAM Access Times: 9 ns for Tag RAM Match 8 ns for Data RAM Decoupling Capacitors for Each Fast Static RAM High Quality Multi-Layer FR4 PWB With Separate Power and Ground Planes 178 Pin Card Edge Module Burndy Connector, Part Number: ELF178KSC-3Z50
MPC2104P MPC2105P
BurstRAM is a trademark of Motorola. The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2 12/20/96
(c) Motorola, Inc. 1996 MOTOROLA FAST SRAM
MPC2104P*MPC2105P 1
MPC2104P BLOCK DIAGRAM
32K x 32 SRAM 16244 A28 A27 A14 - A26 ADS0 CNTEN0 VSS CG0 CLK0 VDD VSS VDD via 100 SGW SA0 SA1 SW SA SBa - SBd ADSC ADV SE1 G DQa - DQd K VDD LBO SE3 ZZ SE2, ADSP CWE0
VDD
DH0 - DH31 BURSTMODE STANDBY
32K x 32 SRAM SGW SA0 SA1 SW SA SBa - SBd ADSC ADV SE1 G DQa - DQd K VDD LBO SE3 ZZ SE2, ADSP CWE1
VDD
CLK1 VDD VSS VDD via 100
DL0 - DL31 BURSTMODE STANDBY
22 A0 - A13
A14 - A26 TCLR TWE
22 MATCH DIRTYOUT 22
CLK2
VALIDIN DIRTYIN TG
TAG: 16K x 14 + V + D A0 - A12 TT1, E1 TDQ0 - TDQ13 SFUNC, GS, A13 RESET TAH, TAG, TAD WS E2, PWRDN WT VCC VCCQ K MATCH TA, VALIDQ DIRTYQ VALIDD DIRTYD GT
VSS VCC via 100 VCC VDD NC
PD3 J3 PD2 J2 PD1 J1 PD0 J0
MPC2104P*MPC2105P 2
MOTOROLA FAST SRAM
MPC2105P BLOCK DIAGRAM
64K x 32 SRAM 16244 A28 A27 A13 - A26 ADS0 CNTEN0 VSS CG0 CLK0 VDD VSS VDD via 100 SGW SA0 SA1 SW SA SBa - SBd ADSC ADV SE1 G DQa - DQd K VDD LBO SE3 ZZ SE2, ADSP CWE0
VDD
DH0 - DH31 BURSTMODE STANDBY
64K x 32 SRAM SGW SA0 SA1 SW SA SBa - SBd ADSC ADV SE1 G DQa - DQd K VDD LBO SE3 ZZ SE2, ADSP CWE1
VDD
CLK1 VDD VSS VDD via 100
DL0 - DL31 BURSTMODE STANDBY
22 A0 - A12
A13 - A26 TCLR TWE
22 MATCH DIRTYOUT
CLK2
22
VALIDIN DIRTYIN TG
TAG: 16K x 14 + V + D A0 - A13 TT1, E1 TDQ0 - TDQ12 SFUNC, GS RESET TAH, TAG, TAD WS E2, PWRDN WT VCC VCCQ K MATCH TA, VALIDQ DIRTYQ TDQ13 VALIDD DIRTYD GT
VSS VCC via 100 VCC VDD NC 4.7K VSS
PD3 J3 PD2 J2 PD1 J1 PD0 J0
MOTOROLA FAST SRAM
MPC2104P*MPC2105P 3
PIN ASSIGNMENT 178-LEAD DIMM
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Name VSS PD0/IDSCLK PD2 DH30 DH28 DH26 DH24 VDD NC DH22 DH20 DH19 VSS DH17 NC DH15 DH12 NC DH11 DH9 NC DH7 VDD DH5 DH3 DH2 Pin 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Name DH0 NC VSS CLK1 VSS DL28 DL26 DL24 NC NC DL22 DL20 DL18 DL16 VSS NC DL14 DL12 DL11 VSS DL9 NC DL7 DL4 VDD DL3 Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Name DL1 DL0 VSS CLK2 VSS NC CG0 NC VDD NC RESERVED ADS0 NC A28 A26 A25 A23 VSS A21 A19 A17 A13 VDD A12 A11 A9 Pin 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Name VSS A7 A5 A3 A0 VCC TCLR MATCH TG DIRTYIN VSS VSS PD1/IDSDATA PD3 DH31 DH29 DH27 DH25 VDD NC DH23 DH21 DH18 VSS DH16 NC Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Name DH14 DH13 NC DH10 DH8 NC DH6 VDD DH4 VSS CLK0 VSS DH1 NC DL31 DL30 VSS DL29 DL27 DL25 NC NC DL23 DL21 DL19 VSS Pin 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Name DL17 NC DL15 DL13 VSS DL10 DL8 CWE1 DL6 VDD DL5 DL2 VSS NC VSS NC VSS CWE0 NC VDD NC RESERVED CNTEN0 NC A27 A24 Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 Name A22 A20 VSS A18 A16 A15 A14 VDD A10 A8 A6 VSS A4 A2 A1 BURSTMODE VCC VALIDIN TWE STANDBY DIRTYOUT VSS
NOTE: VCC and VDD must be connected on all modules.
TOP VIEW - CASE TBD
90 1
131 132
42 43
154 155
65 66
178
89
MPC2104P*MPC2105P 4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations 66, 67, 68, 69, 71, 72, 73, 74, 76, 77, 78, 80, 81, 82, 83, 155, 156, 157, 158, 160, 161, 162, 163, 165, 166, 167, 169, 170, 171 64 172 59 30, 56, 115 153 138, 148 4, 5, 6, 7, 10, 11, 12, 14, 6, 17, 19, 20, 22, 24, 25, 26, 27, 93, 94, 95, 96, 99, 100, 101, 103, 105, 106, 108, 109, 111, 113, 117 88 177 32, 33, 34, 37, 38, 39, 40, 43, 44, 45, 47, 49, 50, 52, 53, 54, 119, 120, 122, 123, 124, 127, 128, 129, 131, 133, 134, 136, 137, 139, 141, 142 86 2 91 3, 92 63, 152 176 85 87 175 174 84, 173 8, 23, 51, 61, 75, 97, 112, 140, 150, 164 1, 13, 29, 31, 41, 46, 55, 57, 70, 79, 89, 90, 102, 114, 116, 121, 130, 135, 143, 145, 147, 159, 168, 178 9, 15, 18, 21, 28, 35 - 36, 42, 48, 58, 60, 62, 65, 98, 104, 107, 110, 118, 125 - 126, 132, 144, 146, 149, 151, 154 Symbol A0 - A28 Type Input Description Address Inputs -- (MSB:0, LSB:28).
ADS0 BURSTMODE CG0 CLK0 - CLK2 CNTEN0 CWE0 - CWE1 DH0 - DH31
Input Input Input Input Input Input I/O
Data RAM Address Strobe. Burstmode. 0 = Linear, 1 = Interleaved. Data RAM Output Enable. Clock Inputs -- CLK2 is for Tag RAM, CLK0 and CLK1 are for Data RAMs only. Data RAM Count Enable. Data RAM Write Enables -- (MSB:0, LSB:1). High Data Bus -- (MSB:0, LSB:31).
DIRTYIN DIRTYOUT DL0 - DL31
Input Output I/O
Dirty input bit. Dirty output bit. Low Data Bus -- (MSB:0, LSB:31).
MATCH PD0/IDSCLK PD1/IDSDATA PD2, PD3 RESERVED STANDBY TCLR TG TWE VALIDIN VCC VDD VSS
Output Input I/O Output
Tag RAM active high match indication. Presence detect bit 0/EEPROM serial clock. (EEPROM option only). Presence detect bit 1/EEPROM serial data. (EEPROM option only). Presence detect bits. Reserved pin.
Input Input Input Input Input Input Input Input
Standby pin. Reduces standby power consumption. Tag RAM clear. Tag RAM output enable. Tag RAM write enable. Tag RAM valid bit. + 5 V power supply. Must be connected. + 3.3 V power supply. Must be connected. Ground.
NC
--
There is no connection to the module.
MOTOROLA FAST SRAM
MPC2104P*MPC2105P 5
TRUTH TABLE (See Notes 1 through 4)
Next Cycle Deselect Begin Read Continue Read Continue Read Suspend Read Suspend Read Begin Write Continue Write Suspend Write Address Used None External Next Next Current Current External Next Current Standby 1 0 X X X X 0 X X ADS0 0 0 1 1 1 1 0 1 1 CNTEN0 X X 0 0 1 1 X 0 1 CG0 2 X X 1 0 1 0 X X X DHx/DLx High-Z High-Z High-Z DQ High-Z DQ High-Z High-Z High-Z CWEx 2 X 14 1 1 1 1 0 0 0
NOTES: 1. X = Don't Care. 1 = logic high. 0 = logic low. 2. CG0 is an asynchronous signal and is not sampled by the clock CLK0. CG0 drives the bus immediately (tGLQX) following CG0 going low. 3. On write cycles that follow read cycles, CG0 must be negated prior to the start of the write cycle to ensure proper write data setup times. CG0 must also remain negated at the completion of the write cycle to ensure proper write data hold times. 4. This READ assumes the RAM was previously deselected.
ASYNCHRONOUS TRUTH TABLE
Operation Read Read Write Deselected Sleep CG0 L H X X X I/O Status Data Out (DHx/DLx) High-Z High-Z High-Z High-Z
LINEAR BURST ADDRESS TABLE (Burst Mode = VSS)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (Burst Mode = VDD)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
MPC2104P*MPC2105P 6
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Tag Data RAM Tag Data RAM Tag Data RAM Symbol VCC VDD Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to + 4.6 - 0.5 to VCC + 0.5 - 0.5 to VDD + 0.5 20 30 3.86 - 10 to + 85 0 to +70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, VDD = 3.3 V + 10%, - 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VDD VIH VIL Min 4.75 3.135 2.2 - 0.5* Max 5.25 3.60 VDD + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA. ** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width 20 ns) for I 20.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VDD) Output Leakage Current (CG = VIH, Vout = 0 to VDD) TTL Output Low Voltage (IOL = + 8.0 mA) TTL Output High Voltage (IOH = - 4.0 mA) Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 1.0 0.4 -- Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Supply Current (CG = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time 20 ns) MPC2104P MPC2105P Symbol IDDA ICCA AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL or VIH VIL = 0.0 V and VIH 3.0 V, Cycle Time 20 ns) MPC2104P MPC2105P ISB1 (VDD) ISB1 (VCC) Max 410 700 320 210 240 320 Unit mA mA mA mA
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance (A13 - A28) (Data RAM Control Pins) (CLK0 - CLK2) (Tag Control Pins) (MATCH, DIRTYOUT) (DH0 - DH31, DL0 - DL31) (A0 - A11) Symbol Cin Max 15 10 5 5 7 8 7 Unit pF
Tag Output Capacitance Data RAM Input/Output Capacitance Tag Input/Output Capacitance
Cout CI/O CI/O
pF pF pF
MOTOROLA FAST SRAM
MPC2104P*MPC2105P 7
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, VDD = 3.3 V + 10%, - 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted
SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MPC2104P/5P Parameter P Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Times: Address Address Status Data In Write Address Advance Chip Enable Address Address Status Data In Write Address Advance Chip Enable Symbol S bl tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tSVKH tDVKH tWVKH tBAVVKH tEVKH tKHAX tKHTSX tKHDX tKHWX tKHBAX tKHEX Min 15 -- -- 0 2 0 -- 2 5 5 2.5 Max -- 8 6 -- -- -- 8 8 -- -- -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 4 3 Notes N
Hold Times:
0.5
--
ns
4
NOTES: 1. All read and write cycle timings are referenced from CLK or CG0. 2. CG is a don't care when CWEx is sampled low. 3. Maximum access times are guaranteed for all possible PowerPC external bus cycles. 4. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever ADS0 is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADS0 is low) to remain enabled.
MPC2104P*MPC2105P 8
MOTOROLA FAST SRAM
READ/WRITE CYCLES
tKHKH CLKx tKHKL tKLKH
MOTOROLA FAST SRAM
A B C D ADS0 CWEx t KHQV COE0 DQx tKHQZ tKHQX1 Q(n-1) Q(A) Q(B) tKHQX2 Q(B+1) Q(B+2) Q(B+3) tGHQZ D(C) D(C+1) D(C+2) D(C+3) D(D) DESELECTED SINGLE READ BURST READ BURST WRITE
A14 - A26
CNTEN0
STANDBY
t KHQV
MPC2104P*MPC2105P 9
SINGLE WRITE
TAG RAM
RESET FUNCTION TRUTH TABLE (See Notes 1 and 2)
TCLR L L CLK L-H L-H TWE H L TAG0 - TAG11 High-Z -- DIRTYOUT L(3) -- MATCH L(3) -- Operation Reset Status Not Allowed POWER Active --
NOTES: 1. H = VIH, L = VIL, X = don't care, -- = undefined. 2. TG is X for this table. 3. These are output states.
READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3)
TG L H TWE H X CLK X X TAG0 - TAG11 Dout High-Z VALIDIN -- -- DIRTYIN -- -- DIRTYOUT Dout -- MATCH Dout -- Operation Read Tag I/O Tag I/O Disable
WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2)
TG H L TWE L L CLK L-H L-H TAG0 - TAG11 Din -- VALIDIN -- -- DIRTYIN -- -- DIRTYOUT -- -- MATCH L -- Operation Write Tag I/O Not Allowed
NOTES: 1. H = VIH, L = VIL, X = don't care, -- = undefined. 2. This table applies when RESET and PWRDN are high. 3. Dout in this case is the same as Din. The input data is written through to the outputs during the write operation.
MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4)
TG X L H H H TWE X H L H H TAG0 - TAG11 -- Dout Din TAGin TAGin VALIDIN(4) -- -- Din L H DIRTYIN(4) -- -- Din -- -- MATCH Dout L L L H Operation Selected Read Tag I/O Write Tag I/O, Status Bits Invalid Data -- Dedicated Status Bits Match -- Dedicated Status Bits
NOTES: 1. H = VIH, L = VIL, X = don't care, -- = undefined. 2. M = high if TAGin equals the memory contents at the address; M = low if TAGin does not equal the contents at that address. 3. PWRDN and RESET are high for this table. GS and CLK are X. 4. This column represents the stored memory cell data for the given status bit at the selected address.
MPC2104P*MPC2105P 10
MOTOROLA FAST SRAM
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . Figure 1a Unless Otherwise Noted
TAG RAM READ CYCLE (See Notes 1 through 4)
Tag RAM Parameter P Clock Access Time Output Enable to Output Valid Output Enable to Output Active Output Disable to Q High-Z Status Bit Hold from Address Change Address Access Time Status Bits Tag Bit Hold from Address Change Address Access Time Tag Bits Symbol S bl tKHQV tGLQV tGLQX tGHQZ tAXSX tAVSV tAVQX tAVQV Min -- -- 0 1 3 -- 3 -- Max 10 8 -- 6 -- 10 -- 12 Unit Ui ns ns ns ns ns ns ns ns
NOTES: 1. Setup and hold times, W (write) refers to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag reads are asynchronous.
TAG RAM WRITE CYCLE (See Notes 1 through 4)
Tag RAM Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock High to Output Active Setup Times Hold Times Status Output Hold Clock High to Status Bits Valid Address Write Address Write Symbol S bl tKHKH tKHKL tKLKH tKHQX tAVKH tWVKH tKHAX tKHWX tKHSX tKHSV Min 15 4.5 4.5 1.5 3 1.5 0 -- Max -- -- -- -- -- -- -- 9 Unit Ui ns ns ns ns ns ns ns ns
NOTES: 1. Setup and hold times, W (write) refers to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag writes are synchronous.
MOTOROLA FAST SRAM
MPC2104P*MPC2105P 11
TAG RAM WRITE AND READ CYCLES(See Note 2)
STATUS WRITE TAG WRITE TAG READ AFTER WRITE TAG READ AFTER READ
CLK t KLKH t KHKH
MPC2104P*MPC2105P 12
VALID t AVKH t WVKH t KHWX t KHAX VALID VALID t AVQV t AXQX t WVKH t KHQV t KHQX (SEE NOTE 1) t GHQZ (SEE NOTE 1) t KHWX t GLQV t GLQX t AVKH VALID INPUT t AVSV t WVKH VALID t KHSV t KHSX VALID VALID VALID t KHWX t AXSX t KHAX VALID OUTPUT VALID OUTPUT t AVSV t AXSX
t KHKL
A14 - A26
TWE
TG
A0 - A13
VALID OUTPUT
VALIDIN DIRTYIN
DIRTYOUT
VALID
MOTOROLA FAST SRAM
NOTES: 1. Transition is measured plus or minus 200 mV from steady state. 2. TCLR = High.
TAG RAM MATCH CYCLE
Tag RAM Parameter P Clock High Write to MATCH Invalid Clock High Read to MATCH Valid Address Valid to MATCH Valid MATCH Valid Hold from Address Change TG Low to MATCH Invalid TG High to MATCH Valid Symbol S bl tKHML tKHMV tAVMV tAXMX tGLML tGHMX Min -- -- -- 2 -- -- Max 7 10 10 -- 7 8 Unit Ui ns ns ns ns ns ns
TAG RAM RESET (TCLR) CYCLE
Tag RAM Parameter P TCLR Setup Time TCLR Hold Time Status Bit Reset Time Status Bit Hold from TCLR Low TCLR Low to MATCH Invalid TCLR High to MATCH Valid TCLR Low to TAG High-Z TCLR High to TAG Active STANDBY Setup to TCLR Low TCLR High to TWE Low Symbol S bl tSTC tHTC tSRST tSHRS tRSML tRSMV tRSQZ tRSQX tPDSR tRHWX Min 4 1 -- 2 -- -- -- -- 30 80 Max -- -- 60 -- 10 100 10 100 -- -- Unit Ui ns ns ns ns ns ns ns ns ns ns
+5 V Z0 = 50 OUTPUT 50 VL = 1.5 V OUTPUT 255 5 pF 480
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
(a)
(b)
Figure 1. Test Loads
MOTOROLA FAST SRAM
MPC2104P*MPC2105P 13
MPC2104P*MPC2105P 14
TAG RAM MATCH CYCLE
VALID ADDRESS VALID MATCH DATA FROM: PROCESSOR t WVKH t KHWX t KHWX t WVKH t WVKH TAG RAM PROCESSOR t GLML t KHML MATCH VALID t KHMV VALID VALID t GLMX
CLK
A14 - A26*
t AVMV t AXMX
A0 - A13
TWE
TG
MATCH
VALID
MOTOROLA FAST SRAM
*Cache addresses used are: A14 - A26 for MPC2104P.
TAG RAM TCLR FUNCTION
CLK tSTC TCLR tSHRS DIRTYOUT tWVKH TWE tRHWX tSRST tHTC
tRSMV MATCH tRSQZ* A0 - A13 * Transition is measured plus or minus 200 mV from steady state. tRSQX VALID
ORDERING INFORMATION
(Order by Full Part Number)
MPC
Motorola Memory Prefix Part Number
2104P 2105P
XX
XX
Speed (66 = 66 MHz) Package (DG = Gold Pad DIMM)
Full Part Numbers -- MPC2104PDG66 MPC2105PDG66
MPC2104P = 256KB, synchronous pipelined MPC2105P = 512KB, synchronous pipelined
MOTOROLA FAST SRAM
MPC2104P*MPC2105P 15
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 303-675-2140 or 1-800-441-2447 MfaxTM: RMFAX0@email.sps.mot.com -- TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MPC2104P*MPC2105P 16
MPC2104P/D MOTOROLA FAST SRAM

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